1. Field of the Invention
The invention relates to a semiconductor device fabricating method, and more particularly to a semiconductor device fabricating method of integrating different devices having different gate insulating layer thicknesses.
2. Description of the Related Art
System-on-a-chip (SoC) designs have become mainstream designs of integrated circuits due to improving semiconductor device scaling processes and critical requirements for dimensions and functions of consumer products. System-on-a-chip (SoC) technology, incorporates all necessary electronic devices and circuitry together, such as, logic devices, memory devices or input/output (I/O) interfaces, for a complete “system” on a single integrated circuit (IC). For example, an SoC fabricating process of a liquid crystal display (LCD) is needed for integrating high voltage (such as, 30 or 40 V) metal oxide semiconductor transistors (HVMOS), low voltage or medium voltage (such as, 2.5 or 5V) logic circuits, or non-volatile memory devices in one chip. Gate insulating layers for SoC devices may have different thicknesses and obvious thickness differences. In the conventional semiconductor fabrication processes, an etching process can be used to remove the remaining gate insulating layers which are not covered by the gates of different devices with different thicknesses after the gate formation step. However, following the conventional etching process steps, undesired substrate loss or gate defect problem due to extreme thickness differences among the gate insulating layers of the different devices, may occur. Therefore, negatively effecting device performances and reliability. Meanwhile, the remaining gate insulating layers of different devices can be respectively removed using additional photolithography and etching processes. However, fabrication costs would increase due to an increase in the number of masks used for the additional photolithography and etching processes.
Therefore, improving device performance and reliability through process integration of different devices having different gate insulating layer thicknesses, such as, high voltage devices, low voltage or medium voltage devices, has become an important challenge.
A novel semiconductor device fabricating method integrating different devices is desirable.